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1 ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 1005, rev. g cat24wc03/05 2k/4k-bit serial eeprom with partial array write protection * catalyst semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. pin configuration block diagram pin functions pin name function a0, a1, a2 device address inputs sda serial data/address scl serial clock wp write protect v cc +1.8v to +5.5v power supply v ss ground dip package (p, l, gl) tssop package (u, y, gy) features 400 khz i 2 c bus compatible* 1.8 to 5.5 volt operation low power cmos technology write protect feature ?op 1/2 array protected when wp at v ih 16-byte page write buffer self-timed write cycle with auto-clear 1,000,000 program/erase cycles 100 year data retention 8-pin dip, 8-pin soic, 8-lead msop and 8-pin tssop package commercial, industrial and automotive temperature ranges "green" package options available description the cat24wc03/05 is a 2k/4k-bit serial cmos eeprom internally organized as 256/512 words of 8 bits each. catalysts advanced cmos technology sub- stantially reduces device power requirements. the cat24wc03/05 features a 16-byte page write buffer. the device operates via the i 2 c bus serial interface, has a special write protection feature, and is available in 8- pin dip or 8-pin soic packages. 8 7 6 5 v cc wp scl sda a 2 a 0 a 1 1 2 3 4 v ss soic package (j, w, gw) a 2 a 0 a 1 v ss 1 2 3 4 8 7 6 5 v cc wp scl sda a 0 v cc wp scl sda 1 2 3 4 8 7 6 5 a 1 a 2 v ss a 2 a 0 a 1 v ss 1 2 3 4 8 7 6 5 v cc wp scl sda msop package (r, z, gz) d out ack sense amps shift registers control logic word address buffers start/stop logic state counters slave address comparators e 2 prom v cc external load column decoders xdec data in storage high voltage/ timing control v ss wp scl a 0 a1 a2 sda not recommended for new design, replace with cat24c03/05
cat24wc03/05 2 doc. no. 1005, rev. g ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice absolute maximum ratings* temperature under bias ................. C55 c to +125 c storage temperature ....................... C65 c to +150 c voltage on any pin with respect to ground (1) ........... C2.0v to +v cc + 2.0v v cc with respect to ground ............... C2.0v to +7.0v package power dissipation capability (ta = 25 c) .................................. 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. d.c. operating characteristics v cc = +1.8v to +5.5v, unless otherwise specified. limits symbol parameter min typ max units test conditions i cc power supply current 3 ma f scl = 100 khz i s (5) standby current (v cc = 5.0v) 0 av in = gnd or v cc i li input leakage current 10 av in = gnd to v cc i lo output leakage current 10 av out = gnd to v cc v il input low voltage C1 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage (v cc = 3.0v) 0.4 v i ol = 3 ma v ol2 output low voltage (v cc = 1.8v) 0.5 v i ol = 1.5 ma note: (1) the minimum dc input voltage is C0.5v. during transitions, inputs may undershoot to C2.0v for periods of less than 20 ns. ma ximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc + 2.0v for periods of less than 20ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) these parameters are tested initially and after a design or process change that affects the parameter according to appropria te aec-q100 and jedec test methods. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C1v to v cc +1v. (5) standby current (i sb ) = 0 a (<900na). capacitance t a = 25 c, f = 1.0 mhz, v cc = 5v symbol test max units conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (a0, a1, a2, scl, wp) 6 pf v in = 0v reliability characteristics symbol parameter min. max. units n end (3) endurance 1,000,000 cycles/byte t dr (3) data retention 100 years v zap (3) esd susceptibility 2000 volts i lth (3)(4) latch-up 100 ma
cat24wc03/05 3 doc. no. 1005, rev. g ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice a.c. characteristics v cc = +1.8v to +5.5v, unless otherwise specified. read & write cycle limits note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. write cycle limits symbol parameter min typ max units t wr write cycle time 10 ms power-up timing (1)(2) symbol parameter max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms l o b m y sr e t e m a r a p 8 . 1 - x x c w 4 2 t a cx x c w 4 2 t a c s t i n u v 5 . 5 - v 8 . 1v 5 . 5 - v 5 . 2v 5 . 5 - v 5 . 4 . n i m. x a m. n i m. x a m. n i m. x a m f l c s y c n e u q e r f k c o l c0 0 10 0 10 0 4z h k t i ) 1 ( t a t n a t s n o c e m i t n o i s s e r p p u s e s i o n s t u p n i a d s , l c s 0 0 20 0 20 0 2s n t a a k c a d n a t u o a t a d a d s o t w o l l c s t u o 5 . 35 . 31 s t f u b ) 1 ( e r o f e b e e r f e b t s u m s u b e h t e m i t t r a t s n a c n o i s s i m s n a r t w e n a 7 . 47 . 42 . 1 s t a t s : d h e m i t d l o h n o i t i d n o c t r a t s446 . 0 s t w o l d o i r e p w o l k c o l c7 . 47 . 42 . 1 s t h g i h d o i r e p h g i h k c o l c446 . 0 s t a t s : u s e m i t p u t e s n o i t i d n o c t r a t s ) n o i t i d n o c t r a t s d e t a e p e r a r o f ( 7 . 47 . 46 . 0 s t t a d : d h e m i t d l o h n i a t a d000s n t t a d : u s e m i t p u t e s n i a t a d0 50 50 5s n t r ) 1 ( e m i t e s i r l c s d n a a d s113 . 0 s t f ) 1 ( e m i t l l a f l c s d n a a d s0 0 30 0 30 0 3s n t o t s : u s e m i t p u t e s n o i t i d n o c p o t s446 . 0 s t h d e m i t d l o h t u o a t a d0 0 10 0 10 0 1s n
cat24wc03/05 4 doc. no. 1005, rev. g ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice functional description the cat24wc03/05 supports the i 2 c bus data trans- mission protocol. this inter-integrated circuit bus proto- col defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. data transfer is controlled by the master device which generates the serial clock and all start and stop conditions for bus access. the cat24wc03/05 operates as a slave device. both the master and slave devices can operate as either transmitter or receiver, but the master device controls which mode is activated. a maximum of 8 devices (24wc03) and 4 devices (24wc05) may be connected to the bus as determined by the device address inputs a0, a1, and a2. pin descriptions scl: serial clock the cat24wc03/05 serial clock input pin is used to clock all data transfers into or out of the device. this is an input pin. sda: serial data/address the cat24wc03/05 bidirectional serial data/address pin is used to transfer data into and out of the device. the sda pin is an open drain output and can be wire-ored with other open drain or open collector outputs. a0, a1, a2: device address inputs these inputs set device address when cascading mul- tiple devices. when these pins are left floating the default values are zeros. a maximum of eight devices can be cascaded when using the cat24wc03. all three address pins are used for cat24wc03. if only one cat24wc03 is addressed on the bus, all three address pins (a0, a1, and a2) can be left floating or connected to v ss . figure 2. write cycle timing figure 1. bus timing figure 3. start/stop timing
cat24wc03/05 5 doc. no. 1005, rev. g ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice a total of four devices can be addressed on a single bus when using the cat24wc05 device. only a1 and a2 address pins are used with this device. the a0 address pin is a no connect pin and can be tied to v ss or left floating. if only one cat24wc05 is being addressed on the bus, the address pins (a1 and a2) can be left floating or connected to v ss . wp: write protect if the wp pin is tied to v cc the upper half of memory array becomes write protected (read only)(locations 80h to ffh for the cat24wc03 and locations 100h to 1ffh for the cat24wc05). when the wp pin is tied to v ss or left floating normal read/write operations are allowed to the device. i 2 c bus protocol the following defines the features of the i 2 c bus protocol: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat24wc03/05 monitor the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the bus master begins a transmission by sending a start condition. the master then sends the address of the particular slave device it is requesting. the four most significant bits of the 8-bit slave address are fixed as 1010 for the cat24wc03/05 (see fig. 5). the next three significant bits (a2, a1, a0) are the device address bits and define which device or which part of the device the master is accessing. up to eight cat24wc03 and four cat24wc05 can be individually addressed by the system. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, a read operation is selected, and when set to 0, a write operation is selected. after the master sends a start condition and the slave address byte, the cat24wc03/05 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. the cat24wc03/05 then performs a read or write operation depending on the state of the r/ w bit. acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. figure 4. acknowledge timing figure 5. slave address bits acknowledge 1 start scl from master 89 data output from transmitter data output from receiver * a0, a1 and a2 correspond to pin 1, pin 2 and pin 3 of the device. ** a8 corresponds to the address of the memory array address word. ***a0, a1 and a2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3). 1 0 1 0 a2 a1 a0 r/w 1 0 1 0 a2 a1 a8 r/w 24wc03 24wc05
cat24wc03/05 6 doc. no. 1005, rev. g ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice the cat24wc03/05 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. when the cat24wc03/05 is in a read mode it transmits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this acknowledge, the cat24wc03/05 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. write operations byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/ w bit set to zero) to the slave device. after the slave generates an acknowledge, the master sends the byte address that is to be written into the address pointer of the cat24wc03/05. after receiving another acknowledge from the slave, the master device transmits the data byte to be written into the addressed memory location. the cat24wc03/05 acknowledge once more and the master generates the stop condition, at which time the device begins its internal programming cycle to nonvolatile memory. while this internal cycle is in progress, the device will not respond to any request from the master device. page write the cat24wc03/05 writes up to 16 bytes of data in a single write cycle, using the page write operation. the page write operation is initiated in the same manner as the byte write operation; however, instead of terminating after the initial word is transmitted, the master is allowed to send up to 15 additional bytes. after each byte has been transmitted, the cat24wc03/05 will respond with an acknowledge and internally increment the low order address bits by one. the high order bits remain unchanged. if the master transmits more than 16 bytes prior to sending the stop condition, the address counter wraps around, and previously transmitted data will be overwritten. once all 16 bytes are received and the stop condition has been sent by the master, the internal programming cycle begins. at this point all received data is written to the cat24wc03/05 in a single write cycle. acknowledge polling the disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the hosts write operation, the cat24wc03/05 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the cat24wc03/05 is still busy with the write operation, no ack will be returned. if the cat24wc03/05 has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. figure 7. page write timing byte address slave address s data s t o p p bus activity: master sda line s t a r t figure 6. byte write timing bus activity: master sda line data n+p byte address (n) a c k a c k data n a c k s t o p s a c k data n+1 a c k s t a r t p slave address note: in this example n = xxxx 0000(b); x = 1 or 0
cat24wc03/05 7 doc. no. 1005, rev. g ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice write protection the write protection feature allows the user to protect against inadvertent programming of the memory array. if the wp pin is tied to v cc , the upper half (locations 80h to ffh for cat24wc03 and locations 100h to 1ffh for cat24wc05) of the memory array is protected and becomes read only. the cat24wc03/05 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the devices failure to send an acknowledge after the first byte of data is received. read operations the read operation for the cat24wc03/05 is initiated in the same manner as the write operation with the one exception that the r/ w bit is set to a one. three different read operations are possible: immediate address read, selective read and sequential read. immediate address read the cat24wc03/05 address counter contains the address of the last byte accessed incremented by one. in other words, if the last read or write access was to address n, the read immediately following would access data from address n+1. if n=e (where e = 255 for the cat24wc03 and 511 for the cat24wc05), then the counter will wrap around to address 0 and continue to clock out data. after the cat24wc03/05 receives its slave address information (with the r/ w bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. the master device does not send an acknowledge but will generate a stop condition. selective read selective read operations allow the master device to select at random any memory location for a read operation. the master device first performs a dummy write operation by sending the start condition, slave address and byte address of the location it wishes to read. after the cat24wc03/05 acknowledge the word address, the master device resends the start condition and the slave address, this time with the r/ w bit set to one. the cat24wc03/05 then responds with its acknowledge and sends the 8-bit byte requested. the master device does not send an acknowledge but will generate a stop condition. figure 8. immediate address read timing scl sda 8th bit stop no ack data out 89 slave address s a c k data n o a c k s t o p p bus activity: master sda line s t a r t figure 9. selective read timing slave address s a c k n o a c k s t o p p bus activity: master sda line s t a r t byte address (n) s a c k data n slave address a c k s t a r t
cat24wc03/05 8 doc. no. 1005, rev. g ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice figure 10. sequential read timing bus activity: master sda line data n+x data n a c k a c k data n+1 a c k s t o p n o a c k data n+2 a c k p slave address sequential read the sequential read operation can be initiated by either the immediate address read or selective read operations. after the cat24wc03/05 sends the initial 8- bit byte requested, the master will respond with an acknowledge which tells the device it requires more data. the cat24wc03/05 will continue to output an 8- bit byte for each acknowledge sent by the master. the operation is terminated when the master fails to respond with an acknowledge, thus sending the stop condition. the data being transmitted from the cat24wc03/05 is outputted sequentially with data from address n followed by data from address n+1. the read operation address counter increments all of the cat24wc03/05 address bits so that the entire memory array can be read during one operation. if more than the e (where e = 255 for the cat24wc03 and 511 for the cat24wc05) bytes are read out, the counter will wrap around and continue to clock out data bytes.
cat24wc03/05 9 doc. no. 1005, rev. g ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice notes: 1. complies with jedec publication 95 ms001 dimensions; however, some of the dimensions may be more stringent. 2. all linear dimensions are in inches and parenthetically in millimeters. 0.180 (4.57) max 0.015 (0.38) 0.100 (2.54) bsc 0.014 (0.36) 0.022 (0.56) 0.245 (6.17) 0.295 (7.49) 0.045 (1.14) 0.060 (1.52) 0.110 (2.79) 0.150 (3.81) 0.120 (3.05) 0.150 (3.81) 0.300 (7.62) 0.325 (8.26) 0.310 (7.87) 0.380 (9.65) 0.355 (9.02) 0.400 (10.16) 8-lead 300 mil wide plastic dip (p, l, gl) 8-lead 150 mil wide soic (j, w, gw) notes: 1. complies with jedec publication 95 ms-012 dimensions; however, some dimensions may be more stringent. 2. all linear dimensions are in inches and parenthetically in millimeters. 0.1497 (3.80) 0.1574 (4.00) 0.2284 (5.80) 0.2440 (6.20) 0.0532 (1.35) 0.0688 (1.75) 0.0040 (0.10) 0.0098 (0.25) 0.050 (1.27) bsc 0.013 (0.33) 0.020 (0.51) 08 0.0075 (0.19) 0.0098 (0.25) 0.0099 (0.25) 0.0196 (0.50) x 45 0.016 (0.40) 0.050 (1.27) 0.1890 (4.80) 0.1968 (5.00)
cat24wc03/05 10 doc. no. 1005, rev. g ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice 8 lead msop (r, z, gz) 0.0150 0.0110 0.38 0.28 0.1970 0.1890 5.00 4.80 s 0.0256 [0.65] bsc 0.1220 0.1142 3.10 2.90 0.0433 [1.10] max. 0.039 [0.10] max. s 0.0059 0.0020 0.15 0.05 s 0.0374 0.0295 0.95 0.75 0.0276 0.0157 0.70 0.40 0.1220 0.1142 3.10 2.90 0? - 6? 0.0091 0.0051 0.23 0.13 0.0118 [0.30] ref. base metal 0.0050 [0.127] 0.0150 0.0110 0.38 0.28 with plating section a - a with plating notes: (1) all dimensions are in mm angles in degrees. 2 does not include mold flash, protrusion or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm. per si de. 3 does not include interlead flash orprotrusion. interlead flash or protrusion shall not exceed 0.25 mm per side. 4 does not include dambar protrusion, allowable dambar protrusion shall be 0.08 mm. (5) this part is compliant with jedec specification mo-187 variations aa. (6) lead span/stand off height/coplanarity are considered as special characteristics. (s) (7) controlling dimensions in inches. [mm]
cat24wc03/05 11 doc. no. 1005, rev. g ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice 8-lead tssop (u, y, gy)
cat24wc03/05 12 doc. no. 1005, rev. g ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice notes: (1) the device used in the above example is a cat24wc03ji-1.8te13 (soic, industrial temperature, 1.8 volt to 5.5 volt operating voltage, tape & reel) ordering information prefix device # suffix 24wc03 j i te13 product number 24wc03: 2k 24wc05: 4k tape & reel operating voltage blank: 2.5v - 5.5v 1.8: 1.8v - 5.5v -1.8 cat optional company id package p: pdip j: soic, jedec r: msop u: tssop l: pdip (lead-free, halogen-free) w: soic, jedec (lead-free, halogen-free) z: msop (lead-free, halogen-free) y: tssop (lead-free, halogen-free) gl: pdip (lead-free, halogen-free, nipdau lead plating) gw: soic, jedec (lead-free, halogen-free, nipdau lead plating) gz: msop (lead-free, halogen-free, nipdau lead plating) gy: tssop (lead-free, halogen-free, nipdau lead plating) rev-c die revision 24wc03: c 24wc05: a temperature range blank = commercial (0 c to 70 c) i = industrial (-40 c to 85 c) a = automotive (-40 c to 105 c) e = extended (-40 c to 125 c)
cat24wc03/05 13 doc. no. 1005, rev. g ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice revision history e t a dn o i s i v e rs t n e m m o c 1 0 0 2 / 4 2 / 7a e u s s i l a i t i n i 4 0 0 2 / 3 / 2b e e s . s n g i s e d w e n r o f d e d n e m m o c e r t o n 3 0 c w 4 2 t a c : d e d d a . t e e h s a t a d 3 0 c f 4 2 t a c 4 0 / 8 1 / 4 0c o g o l e e r f d a e l d d a s e r u t a e f e t a d p u n o i t a m r o f n i g n i r e d r o e t a d p u y r o t s i h n o i s i v e r d d a r e b m u n v e r e t a d p u 4 0 / 8 1 / 5 0d e e s . s n g i s e d w e n r o f d e d n e m m o c e r t o n 3 0 c w 4 2 t a c : e t e l e d . t e e h s a t a d 3 0 c f 4 2 t a c y r o t s i h n o i s i v e r e t a d p u r e b m u n v e r e t a d p u 4 0 / 7 0 / 6 0e n o i t a m r o f n i g n i r e d r o o t n o i s i v e r e i d d e d d a 5 0 / 2 1 / 8 0f s e r u t a e f e t a d p u s n o i t c n u f n i p e t a d p u s c i t s i r e t c a r a h c y t i l i b a i l e r e t a d p u s c i t s i r e t c a r a h c g n i t a r e p o . c . d e t a d p u s c i t s i r e t c a r a h c . c . a e t a d p u s n o i s n e m i d e g a p d d a n o i t a m r o f n i g n i r e d r o e t a d p u 6 0 / 6 2 / 7 0g 5 0 / 3 0 c 4 2 t a c h t i w e c a l p e r , n g i s e d w e n r o f d e d n e m m o c e r t o n : t r e s n i
copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 minipot catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. catalyst semiconductor, inc. corporate headquarters 2975 stender way santa clara, ca 95054 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com publication #: 1005 revison: g issue date: 07/26/06

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